Pipeline CPU
Utilized assembly programming in Xilinx environment to create and analyze the use of a barebones operational pipeline CPU
Utilized assembly programming in Xilinx environment to create and analyze the use of a barebones operational pipeline CPU
Above, you will see images of the post-project operational waveform & design schematics, while below you can get a glimpse of the I/O & Floor Plans
Above, you will see images of the post-project operational waveform & design schematics, while below you can get a glimpse of the I/O & Floor Plans
This was a particularly interesting project, as working in the Computer Engineering field is somewhat foreign. However, the registry coding was a very different style from any other language i have had experience with.
This was a particularly interesting project, as working in the Computer Engineering field is somewhat foreign. However, the registry coding was a very different style from any other language i have had experience with.